This invention relates generally to digital signal detectors and more specifically to detecting a predetermined quasi-random data sequence. As used herein, a quasi-random data sequence means a predetermined periodic sequence of data which simulates random data.
Although it is possible to generate true random data, a quasi-random sequence often can be utilized in its place such as for a test pattern utilized to verify the operation of a data network. The quasi-random sequence has the advantage that it's predetermined pattern can be compared with a received transmission of the sequence for bit error rate measurement.
Quasi-random generators often comprise series of interconnected flip-flops in which certain selected stages are combined to provide feedback to earlier stages. Such a generator having N stages can generate a digital sequence of 2.sup.N.
One way to detect a quasi-random digital sequence is to store all the bits in one periodic cycle of the quasi-random generator and compare this stored pattern against received data. For quasi-random sequences having a large number of bits this technique either required significant hardware or is computationally intensive if implemented in software.
It is an object of the present invention to provide an improved quasi-random sequence detector which utilizes a minimum of memory cells and associated control logic.